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1. ………………………. can be defined as the design methodology of how computer hardware. components interact based on the challenges imposed by real-world components and technology a) Computer Organization b) Computer Architecture c) Computer Design. d) System Architecture 2. What is the ISA's main function? a) Manages Power Consumption in Hardware b) Interfaces with Peripherals c) Controls Network Connectivity d) Defines the Interface between Software and Hardware 3. The computer's internal memory can be found in/on/within. a) External Storage Devices b) The Central Processing Unit c) The Motherboard d) Cache Memory 4. In sequential access, the process must begin and read through a specific... a) Random Sequence b) Parallel Sequence c) Linear Sequence d) Circular Sequence 5. CISC is to Complex Instruction Set Computer, whilst RISC is to a. Complex Instruction Set Computing b. Reduced Integrated Set Computer c. Reduced Instruction Set Computer d. Random Instruction Set Computer 6. During the third generation of computers, Quantum Computers b. Integrated Circuits c. Supercomputers d. Microprocessors . The extremely fast memory type that acts as a buffer between RAM and the CPU is a. Flash memory b. Virtual memory c. Cache memory d. ROM 13………………………. refers to a design model for computers where the processing unit, memory, and input-output devices are interconnected through a single, central system bus. a. Von Neumann Architecture b. Turing Architecture C. Harvard Architecture d. Moore's Architecture 14. What holds the location in the computer's memory where the CPU needs to access data, instructions, or other information? a. Cache Memory b. Memory Data Register (MDR) c. Memory Address Register (MAR) d. Central Processing Unit (CPU) 15......................... is the process of accumulating instructions from the processor through a pipeline. a. Caching b. Fetching c. Storing d. Pipelining 16. The pipelining process involves ……….. stages of operation. a. 3 b. 4 C. 5 d.6 17 ……………….. occurs when two instructions in a program are to be executed in sequence and both access a particular memory or register operand. a. Data Hazard b. Pipeline Stall c. Data Conflict d. Execution Delay 18. What is used to hold the address of a special chunk of main memory used for temporary storage during program execution? a. Program Counter b. Stack Pointer c. Memory Buffer d. Index Register 19. Which of these is a disadvantage of pipelining as used in computer architecture? a) The cycle time of the Processor is reduced. b) It increases the throughput of the system c) It makes the system reliable. d) The instruction latency is more. 20........................ refers to the time between the start and the completion of a task (in time units). a. Execution Time b. Processing Time c. Response Time d. Cycle Time 21. …………………. is a common pathway to connect various subsystems in a computer system. a. Bus b. Link c. Channel d. Pathway 22. Which of the following best explains th

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  1. ………………………. can be defined as the design methodology of how computer hardware. components interact based on the challenges imposed by real-world components and technology a) Computer Organization b) Computer Architecture c) Computer Design. d) System Architecture
  2. What is the ISA's main function? a) Manages Power Consumption in Hardware b) Interfaces with Peripherals c) Controls Network Connectivity d) Defines the Interface between Software and Hardware
  3. The computer's internal memory can be found in/on/within. a) External Storage Devices b) The Central Processing Unit c) The Motherboard d) Cache Memory
  4. In sequential access, the process must begin and read through a specific... a) Random Sequence b) Parallel Sequence c) Linear Sequence d) Circular Sequence
  5. CISC is to Complex Instruction Set Computer, whilst RISC is to a. Complex Instruction Set Computing b. Reduced Integrated Set Computer c. Reduced Instruction Set Computer d. Random Instruction Set Computer
  6. During the third generation of computers, Quantum Computers b. Integrated Circuits c. Supercomputers d. Microprocessors . The extremely fast memory type that acts as a buffer between RAM and the CPU is a. Flash memory b. Virtual memory c. Cache memory d. ROM 13………………………. refers to a design model for computers where the processing unit, memory, and input-output devices are interconnected through a single, central system bus. a. Von Neumann Architecture b. Turing Architecture C. Harvard Architecture d. Moore's Architecture
  7. What holds the location in the computer's memory where the CPU needs to access data, instructions, or other information? a. Cache Memory b. Memory Data Register (MDR) c. Memory Address Register (MAR) d. Central Processing Unit (CPU) 15......................... is the process of accumulating instructions from the processor through a pipeline. a. Caching b. Fetching c. Storing d. Pipelining
  8. The pipelining process involves ……….. stages of operation. a. 3 b. 4 C. 5 d.6 17 ……………….. occurs when two instructions in a program are to be executed in sequence and both access a particular memory or register operand. a. Data Hazard b. Pipeline Stall c. Data Conflict d. Execution Delay
  9. What is used to hold the address of a special chunk of main memory used for temporary storage during program execution? a. Program Counter b. Stack Pointer c. Memory Buffer d. Index Register
  10. Which of these is a disadvantage of pipelining as used in computer architecture? a) The cycle time of the Processor is reduced. b) It increases the throughput of the system c) It makes the system reliable. d) The instruction latency is more. 20........................ refers to the time between the start and the completion of a task (in time units). a. Execution Time b. Processing Time c. Response Time d. Cycle Time
  11. …………………. is a common pathway to connect various subsystems in a computer system. a. Bus b. Link c. Channel d. Pathway
  12. Which of the following best explains th
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