In this lab, why are the bottom 2 bits of the address lines from the bus bridge always zero?Question 2Select one:a.The bus bridge has been configured for a data width of 32 bits, and memory is halfword addressed.b.The bus bridge has been configured for a data width of 32 bits, and memory is word aligned.c.Trick question! The bottom 2 bits of the address lines from the bus bridge are NOT always zero.d.The bus bridge has been configured for a data width of 16 bits, and memory is word aligned.

With a 2 Mbyte address range and four 16 bit registers to map to this address range in part 1, select the valid approach(es) for this lab. Question 4Select one or more:a.Since the bus bridge is half word aligned, we can choose any 2 address lines apart from address[0] to determine which of the four registers is read or written to.b.Since the bus bridge is word aligned, address[1:0] is a valid choice for determining which of the four registers is read or written to.c.The address[20:17] bits form one of many minimal sets for determining which of the four registers is read or written to.d.We could choose to decode the address[10:9] bits to determine which of the four registers is chosen, even though it might be confusing.

In part 1, the 16 bit word SRAM is interfaced to the 32 bit bus bridge. Which bus bridge address bits should be connected to the SRAM_ADDR[19:1]?  (Note the low order bit of SRAM_ADDR has been deliberately left out here).Question 3Select one:a.address[20:2]b.address[19:2]c.address[18:0]d.address[19:1]e.address[18:1]

A 16-bit address bus is carrying the address4567H and is partially decoded with lines A15and A13 being unused Which one of theseaddresses would access a different hardwarelocation:• (a) E567H.• (b) 4567H.• (c) 6567H.• (d) 8567H.

The number of address lines required to address a 16 MB memory space is:Group of answer choices24182014

Briefly explain the following with respect to the bus interconnection structure of acomputer:i. Address bus.ii. Bus width.