During an SRAM read cycle, the SRAM_DQ signals are driven by the FPGA with read_data.Question 7Select one:TrueFalse

During the SRAM write cycle all outputs of the SRAM_Controller module to the SRAM are a combinational logic function made up of one or more of the bus bridge signals: bus_enable, rw, address and byte_enable.Question 3Select one:TrueFalse

The SRAM_DQ signals are inout type. When should the SRAM_Controller tristate these signals?Question 5Select one:a.When rw=1 and bus_enable=0b.When rw=1 or bus_enable=0c.When rw=1 and bus_enable=1d.When rw=1 or bus_enable=1e.When rw=0 or bus_enable=0

Assume that the arbiter has request inputs and acknowledge outputs. The write_data[31:0] signals that are passed onto the SRAM_Controller module do not depend on the acknowledge outputs of the arbiter.Question 9Select one:TrueFalse

Read-only memory (ROM) chips have information stored in them by the manufacturer.Group startsTrue or FalseTrue, unselectedFalse, unselected

During a read transaction on the bus, two bits of the byte_enable[1:0] signals are required in Part 1 for assigning the read_data[15:0] signals in a bus interface.Question 8Select one:TrueFalse