Draw the logic circuits for below Verilog code snippets.Question 1.always @ (posedge clock)beginq1=m;q2=q1;endQuestion 2.always @ (posedge clock)beginq2=q1;q1=m;end

The Verilog code snippets you provided are describing sequential logic, specifically flip-flops. These are not easily represented as simple logic gates (like AND, OR, NOT), but I can describe the behavior of the circuits.

1. For the first code snippet:

always @ (posedge clock)
begin
q1=m;
q2=q1;
end

This code describes a pair of D flip-flops connected in series. At each positive edge of the clock, the value of 'm' is loaded into 'q1', and the previous value of 'q1' (before the clock edge) is loaded into 'q2'.

2. For the second code snippet:

always @ (posedge clock)
begin
q2=q1;
q1=m;
end

This code also describes a pair of D flip-flops connected in series, but the order of operations is reversed. At each positive edge of the clock, the value of 'q1' is loaded into 'q2', and then the value of 'm' is loaded into 'q1'.

In both cases, the circuits would look like two D flip-flops with the output of the first connected to the input of the second. The difference is in the order that the flip-flops are updated in response to the clock edge.