On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________*The clock pulse is LOWThe clock pulse is HIGHThe clock pulse transitions from LOW to HIGHThe clock pulse transitions from HIGH to LOW

A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________a 20 kHz square wavea 10 kHz square waveconstantly HIGHconstantly LOW

When does a negative level-triggered flip-flop changes its state?Select one:1.When the clock is negative2.When the clock is positive3.When the inputs are all zero4.When the inputs are all one

Observe the sequential circuit in Fig. 1. Which of the following is a possible correct waveform of the output? All used D flip-flops are positive edge triggered, Q0 is initially PRESET and Q1 CLEARED.

Asynchronous inputs will cause the flip-flop to respond immediately with regard to the clock input.(A) True(B) False(C)(D)

What happens to the output of a positive edge triggered flipflop if asynchronous Clear input is activated?Output changes to 1 at the same timeOutput changes to 0 during next positive edgeOutput changes to 0 during next negative edgeOutput changes to 0 at the same time