When a high is applied to the Set line of an NAND Gate SR Latch, the output isa.Q output goes lowb.Q output goes highc.Q' Output goes lowd.It holds the previous state

When a high is applied to the Set line of an NAND Gate SR Latch, the output is:

a. Q output goes low b. Q output goes high c. Q' Output goes low d. It holds the previous state

To determine the correct answer, we need to understand the behavior of an NAND Gate SR Latch when a high is applied to the Set line.

1. An NAND Gate SR Latch consists of two cross-coupled NAND gates.
2. The Set line is connected to one of the inputs of the first NAND gate.
3. The output of the first NAND gate is connected to one of the inputs of the second NAND gate.
4. The output of the second NAND gate is connected to one of the inputs of the first NAND gate.
5. The Q output is taken from the output of the first NAND gate, and the Q' output is taken from the output of the second NAND gate.

Now, let's analyze the behavior when a high is applied to the Set line:

• When the Set line is high, it means that the input of the first NAND gate is low.
• Since one of the inputs of the first NAND gate is low, the output of the first NAND gate will be high.
• The high output of the first NAND gate will be fed back to one of the inputs of the second NAND gate.
• Since one of the inputs of the second NAND gate is high, the output of the second NAND gate will be low.
• The low output of the second NAND gate will be fed back to one of the inputs of the first NAND gate.

Based on this analysis, we can conclude that when a high is applied to the Set line of an NAND Gate SR Latch, the Q output goes high (option b), and the Q' output goes low (option c).