Which of the following loops are supported by verilog?a.if-else loopb.for loopc.All the aboved.while loop
Question
Which of the following loops are supported by verilog?a.if-else loopb.for loopc.All the aboved.while loop
Solution
In Verilog, the supported loops are the 'for' loop. So, the correct answer is b. 'for' loop. The 'if-else' is a conditional statement, not a loop. And 'while' loop is not supported in Verilog.
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