Assume 40% of the instructions are data accessing instruction. Let a hit take 1 clock cycle and the miss penalty is 100 clock cycle. Assume instruction miss rate is 4% and data access miss rate is 12%, what is the average memory access time?

A program uses 1600 instructions. Microprocessor references cache memory for 1493 instructions with ZERO wait states. Each main memory reference requires 3 WAIT states. Calculate the miss rate in the system. Select one:a. 92.33 %b. 6.67 %c. 7.67%d. 93.33 %

A small computer has a direct-mapped data cache of size 1 kilo Bytes. lts block size is 32 bytes, hit time is 2 processor clock cycles, and, the miss penalty is 20 processor clock cyclesWhile running a loop, in each iteration data (of size 1 byte) is accessed from memory addresses 6, 522, 768, 1028. If the loop iterates 10 times, compute the average data access time for the loop.

In this question, we will look at the different ways capacity affects overall performance. In general, cache access time is proportional to capacity. Assume that main miss penalty for both processors take 200 s. The following table shows data for caches attached to each of two processors:   Miss RateHit TimeP18%2sP22%5sWhat is the Average Memory Access Time for P1 and P2?

36)i) A computer with cache access time of 100 ns and hit ratio of 0·9 produces an average access time of

If the average time to handle a page fault is 10 milliseconds, and a memory access requires 1 microsecond, then achieving a 99.99% hit ratio would lead to an average memory access time ofa.1 millisecondb.1.9999 millisecondsc.1.9999 microsecondsd.9.999 microseconds