Write a Verilog code to implement the following given logical function for BCD to Binary codeconverter. Write the corresponding Testbench code for the verification of your Verilog code. Giveninputs as 87

Here is a simple Verilog code for a BCD to Binary converter. This code assumes that the BCD input is valid (i.e., 0-9). If the BCD input can be invalid (i.e., 10-15), you should add error checking code.

module bcd_to_bin (
    input [3:0] bcd,
    output reg [6:0] bin
);

always @* begin
    case (bcd)
        4'h0: bin = 7'b0000000;
        4'h1: bin = 7'b0000001;
        4'h2: bin = 7'b0000010;
        4'h3: bin = 7'b0000011;
        4'h4: bin = 7'b0000100;
        4'h5: bin = 7'b0000101;
        4'h6: bin = 7'b0000110;
        4'h7: bin = 7'b0000111;
        4'h8: bin = 7'b0001000;
        4'h9: bin = 7'b0001001;
        default: bin = 7'b0000000; // error
    endcase
end

endmodule

And here is a simple testbench for the above code:

module test;

    reg [3:0] bcd;
    wire [6:0] bin;

    bcd_to_bin u1 (
        .bcd(bcd),
        .bin(bin)
    );

    initial begin
        $monitor("At time %d, bcd = %b, bin = %b", $time, bcd, bin);

        #10 bcd = 4'h8;
        #10 bcd = 4'h7;
        #10 bcd = 4'h6;
        #10 bcd = 4'h5;
        #10 bcd = 4'h4;
        #10 bcd = 4'h3;
        #10 bcd = 4'h2;
        #10 bcd = 4'h1;
        #10 bcd = 4'h0;
        #10 bcd = 4'h9;
        #10 bcd = 4'hA; // error
        #10 bcd = 4'hB; // error
        #10 bcd = 4'hC; // error
        #10 bcd = 4'hD; // error
        #10 bcd = 4'hE; // error
        #10 bcd = 4'hF; // error

        #10 $finish;
    end

endmodule

This testbench will test all possible BCD inputs and print the BCD input and the corresponding binary output.